module mem_fifo(shift_out, shift_in, clk, res_n, wdata, rdata, full, empty);
input shift_out;
input shift_in;
input clk;
input res_n;
input [DSIZE-1:0] wdata;
output [DSIZE-1:0] rdata;
output full;
output empty;

reg [DSIZE-1:0] wdata;
reg full;
reg empty;



endmodule